MOS Field-Effect Transistors (MOSFETs)

Section 5.1: Device Structure and Physical Operation

5.1

An NMOS transistor is fabricated in a 0.13-μm CMOS process with L = 1.5 L min and W = 1.3 μm. The process technology is specified to have t o x = 2.7 nm, μ n = 4 0 0 cm 2/V·s, and V t n = 0.4 V.
(a) Find C o x, k n ' , and k n.
(b) Find the overdrive voltage V O V and the minimum value of V D S required to operate the transistor in saturation at a current I D = 1 0 0 μA. What gate-to-source voltage is required?
(c) If v D S is very small, what values of V O V and V G S are required to operate the MOSFET as a 2-k resistance? If V G S is doubled, what r D S results? If V G S is reduced, at what value does r D S become infinite?

(a) L   =   1.5 L min = 1.5 × 0.1 3 = 0.1 9 5  μ m C o x = 𝜖 o x t o x  where 𝜖 o x = 3.9  𝜖 0 = 3.9 × 8.8 5 4 × 1 0 1 2 = 3.4 5 × 1 0 1 1  F/m C o x = 3.4 5 × 1 0 1 1  F/m 2.7 × 1 0 9  m = 1.2 8 × 1 0 2  F/m 2 = 1.2 8 × 1 0 2 × 1 0 1 5 × 1 0 1 2  fF∕μ m 2 = 1 2.8  fF∕μ m 2 k n = μ n C o x = 4 0 0  ( cm 2 V·s ) × 1 2.8  ( fF μ m 2 ) = 4 0 0 × 1 0 8  ( μ m 2 V·s ) × 1 2.8 × 1 0 1 5  ( F μ m 2 ) = 5 1 2 × 1 0 6 ( F/V·s ) = 5 1 2 × 1 0 6  ( A/V 2 ) = 5 1 2  μ A/V 2 k n = k n  ( W L ) = 5 1 2 × 1.3 0.1 9 5 = 3 4 1 3  μ A/V 2 k n = 3.4 1 3  mA/V 2
(b) When the MOSFET operates in saturation, we have
I D = 1 2 k n V O V 2
Thus, 1 0 0   =   1 2 × 3 4 1 3 × V O V 2 V O V = 0.2 4  V To operate in saturation, V D S must at least be equal to V O V , thus
V D S min = 0.2 4  V
The gate-to-source voltage is
V G S = V t n + V O V = 0.4 + 0.2 4 = 0.6 4  V
(c) When v D S is small,
i D k n V O V v D S
and
r D S v D S i D = 1 k n V O V
Thus, for r D S = 2  k , 2 × 1 0 3   =   1 3.4 1 3 × 1 0 3 V O V V O V   =   0.1 5  V and, correspondingly,
V G S = 0.4 + 0.1 5 = 0.5 5  V
If V G S is doubled, we obtain
V G S = 2 × 0.5 5 = 1.1  V
and
V O V = 1.1 0.4 = 0.7  V
Thus, correspondingly, r D S becomes r D S   =   1 k n V O V = 1 3.4 1 3 × 1 0 3 × 0.7   =   4 1 8.6  Ω As V G S is reduced, r D S increases, becoming infinite when the channel disappears, which occurs as V O V reaches zero or, correspondingly,
V G S = V t n = 0.4  V

Section 5.2: Current–Voltage Characteristics

5.2

An NMOS transistor fabricated in a 0.13-μm process has L = 0.2 μm and W = 2 μm. The process technology has C o x = 1 2.8 fF/μm 2, μ n = 4 5 0 cm 2/V·s, and V t n = 0.4 V. Neglect the channel-length modulation effect.
(a) If the transistor is to operate at the edge of the saturation region with I D = 1 0 0 μA, find the values required of V G S and V D S.
(b) If V G S is kept constant at the value found in (a) while V D S is changed, find I D that results at V D S equal to half the value in (a) and at V D S equal to 0.1 the value in (a).
(c) To investigate the operation of the MOSFET as a linear amplifier, let the operating point be at V G S = 0.6 V and V D S = 0.3 V. Find the change in i D for v G S changing from 0.6 V by + 1 0 mV and by 1 0 mV. Comment.

(a) When the transistor operates in saturation, we obtain
I D = 1 2 μ n C o x ( W L ) V O V 2
where μ n C o x   =   4 5 ( cm 2 V·s ) × 1 2.8  ( fF/ μ m 2 ) = 4 5 0 × 1 0 8 ( μ m 2 V·s ) × 1 2.8 × 1 0 1 5 ( F/ μ m 2 ) = 5 7 6 × 1 0 6 ( F/V·s ) = 5 7 6   μ A/V 2 To obtain I D = 1 0 0  μ A, V O V can be found from 1 0 0   =   1 2 × 5 7 6 × 2  μ m 0.2  μ m × V O V 2 V O V = 0.1 8 6  V Correspondingly,
V G S = V t n + V O V = 0.4 + 0.1 8 6 = 0.5 8 6  V
At the edge of saturation,
V D S = V D S min = V O V = 0.1 8 6  V
(b) If V D S is lowered below V D S min, the transistor operates in the triode region, thus i D   =   μ n C o x ( W L ) [ ( V G S V t n ) v D S 1 2 v D S 2 ] = 5 7 6 × 2 0.2 ( 0.1 8 6 v D S 0.5 v D S 2 ) For v D S   =   0.5  V D S min = 0.5 × 0.186 = 0.093  V we obtain i D   =   5 7 6 × 1 0 ( 0.1 8 6 × 0.0 9 3 0.5 × 0.0 9 3 2 ) = 7 4.7  μ A For v D S   =   0.1  V D S min = 0.1 × 0.1 8 6 = 0.0 1 8 6  V we get i D   =   5 7 6 × 1 0  ( 0.1 8 6 × 0.0 1 8 6 0.5 × 0.0 1 8 6 2 ) = 1 8.9  μ A (c) For V G S = 0.6 V (i.e., V O V = 0.2 V) and V D S = 0.3 V, the MOSFET will be operating in saturation with I D   =   1 2  μ n C o x ( W L ) V O V 2 = 1 2 × 5 7 6 × 2 0.2 × 0. 2 2 = 1 1 5.2  μ A Now, if v G S is increased by a 10-mV increment, then
v G S = 0.6 + 0.0 1 0 = 0.6 1 0  V
and the current becomes i D   =   1 2 × 5 7 6 × 2 0.2 × ( 0.6 1 0 0.4 ) 2 = 1 2 7 μ A Thus, i D increases by an increment
i D = 1 2 7 1 1 5.2 = 1 1.8  μ A
If v G S is decreased by 10 mV, we obtain
v G S = 0.6 0.0 1 0 = 0.5 9 0  V
and the current becomes i D   =   1 2 × 5 7 6 × 2 0.2 × ( 0.5 9 0 0.4 ) 2 = 1 0 4 μ A Thus, the change in i D is
i D = 1 0 4 1 1 5.2 = 1 1.2 μ A
Observe that the incremental changes in i D are almost equal, indicating that the operation is almost linear. Linearity improves if the incremental changes in v G S are made smaller. (For instance, try v G S = ± 5 mV.)

5.3

Alt text

Figure 5.3.1

An NMOS transistor fabricated in a process for which the process transconductance parameter is 400 μA/V 2 has its gate and drain connected together. The resulting two-terminal device is fed with a current source I as shown in Fig. 5.3.1. With I = 4 0 μA, the voltage across the device is measured to be 0.6 V. When I is increased to 90 μA, the voltage increases to 0.7 V. Find V t and W L of the transistor. Ignore channel-length modulation.

Alt text

Figure 5.3.1

Refer to Fig. 5.3.1 and observe that since V D S = V G S = V t + V O V , we have

V D S > V O V

and thus the MOSFET is operating in the saturation region. Thus, ignoring channel-length modulation, we can write

I D = 1 2 k n W L ( V G S V t ) 2

Substituting the given data, we obtain

4 0 = 1 2 × 4 0 0 × ( W L ) ( 0.6 V t ) 2
(1)

and

9 0 = 1 2 × 4 0 0 × ( W L ) ( 0.7 V t ) 2
(2)

Dividing Eq. (2) by Eq. (1), we obtain

9 4   =   ( 0.7 V t ) 2 ( 0.6 V t ) 2 3 2 = 0.7 V t 0.6 V t

which results in

V t = 0.4  V

Substituting for V t into Eq. (1) gives

4 0   =   2 0 0 × ( W L ) × 0.0 4 W L = 5

5.4

An NMOS transistor for which k n = 4 mA/V 2 and V t = 0.3 5 V is operated with V G S = V D S = 0.6 V. What current results? To what value can V D S be reduced while maintaining the current unchanged? If the transistor is replaced with another fabricated in the same technology but with twice the width, what current results? For each of the two transistors when operated at small V DS, what is the range of linear resistance r D S obtained when V G S is varied over the range 0.5 V to 1 V? Neglect channel-length modulation.

Operation with V D S = V G S = V t + V O V means V D S > V O V and thus the MOSFET is in the saturation region. Thus, neglecting channel-length modulation, we can write for I D,

I D   =   1 2 k n ( V G S V t ) 2 = 1 2 × 4 × ( 0.6 0.3 5 ) 2 = 0.1 2 5  mA

The voltage V D S can be reduced to a value equal to V O V while the MOSFET remains in the saturation region, that is,

V D S min = 0.6 0.3 5 = 0.2 5  V

A transistor having twice the value of W will have twice the value of k n and thus the current will be twice as large, that is,

I D = 2 × 0.1 2 5 = 0.2 5  mA

The linear resistance r D S is given by

r D S = 1 k n ( V G S V t )

With V t = 0.3 5 V and with V G S varying over the range 0.5 V to 1 V, r D S will vary over the range

r D S = 1 0.1 5 k n  to 1 0.6 5 k n

For the first device with k n = 4 mA/V, r D S will vary over the range

r D S = 1 0.1 5 × 4 = 1.6 7  k Ω

to

r D S = 1 0.6 5 × 4 = 0.3 8  k Ω

The wider device has k n = 8 mA/V and thus its r D S will vary over the range

r D S = 0.833   k Ω   to   0.192   k Ω

5.5

An NMOS transistor is fabricated in a 0.13- μm process having k n ' = 5 0 0 μA/V 2, and V A ' = 5 V/ μm.
(a) If L = 0.2 6 μm and W = 2.6 μm, find V A and λ.
(b) If the device is operated at V O V = 0.2 V and V D S = 0.6 5 V, find I D.
(c) Find r o at the operating point specified in (b).
(d) If V D S is increased to 1.3 V, what is the corresponding change in I D? Do this two ways: using the expression for I D and using r o. Compare the results obtained.

(a)

V A   =   V A L = 5 × 0.2 6 = 1.3  V λ = 1 V A = 1 1.3 = 0.7 7  V 1

(b) Since V D S = 0.6 5 V is greater than V O V , the NMOS transistor is operating in saturation. Thus, I D   =   1 2 k n ( W L ) V O V 2 ( 1 + λ V D S ) = 1 2 × 5 0 0 × 2.6 0.2 6 × 0. 2 2 × ( 1 + 0.7 7 × 0.6 5 ) = 1 5 0 μ A

(c)

r o = V A I D '

where I D ' is the drain current without taking channel-length modulation into account, thus

I D '   =   1 2 k n ( W L ) V O V 2 = 1 2 × 5 0 0 × 2.6 0.2 6 × 0. 2 2 = 1 0 0 μ A

Hence,

r o = 1.3  V 1 0 0  μ A = 1.3  V 0.1  mA = 1 3  k Ω

(d) If V D S is increased to 1.3 V, I D becomes

I D   =   1 2 × 5 0 0 × 2.6 0.2 6 × 0. 2 2 ( 1 + 0.7 7 × 1.3 ) = 2 0 0  μ A

That is, I D increases by 50 μ A. Alternatively, we can use r o to determine the increase in I D as

I D   =   V D S r o = 0.6 5  V 1 3  k Ω = 0.0 5  mA = 5 0 μ A

which is identical to the result obtained directly.


5.6

Alt text

Figure 5.6.1

The PMOS transistor in Fig. 5.6.1 has V t p = 0.5 V, k p = 1 0 0 μA/V 2 , and W L = 1 0.
(a) Find the range of v G for which the transistor conducts.
(b) In terms of v G, find the range of v D for which the transistor operates in the triode region.
(c) In terms of v G, find the range of v D for which the transistor operates in saturation.
(d) Find the value of v G and the range of v D for which the transistor operates in saturation with I D = 2 0 μA. Assume λ = 0.
(e) If λ = 0.2 V 1, find r o at the operating point in (d).
(f) For V O V equal to that in (d) and λ = 0.2 V 1, find the value of I D at V D = 1 V and at V D = 0 V. Use these values to calculate the output resistance r o and compare the result to that found in (e).

Alt text

Figure 5.6.1


V t p   =   0.5  V , k p = 1 0 0 μ A/V 2 W L = 1 0

(a) For the transistor to conduct, v G must be lower than v S by at least V t p , that is, by 0.5 V. Thus the transistor conducts for v G 1.8 0.5, or v G 1.3 V.
(b) For the transistor to operate in the triode region, the drain voltage must be higher than the gate voltage by at least V t p volts, thus

v D v G + 0.5  V

(c) For the transistor to operate in the saturation region, the drain voltage cannot exceed the gate voltage by more than V t p , that is,

v D v G + 0.5  V

(d) When the transistor is operating in saturation, we obtain

I D = 1 2 k p ( W L )   V O V 2

Substituting the given values, we obtain

2 0   =   1 2 × 1 0 0 × 1 0 V O V 2 V O V = 0.2  V

which is obtained when

v G   =   V D D V S G = 1.8 - V t p + V O V = 1.8 ( 0.5 + 0.2 ) = 1.1  V

For this value of v G, the range that v D is allowed to have while the transistor remains in saturation is

v D v G + V t p  

that is,

v D 1.6  V

(e)

r o   =   V A I D   =   1 λ I D

where I D is the value of I D without channel-length modulation taken into account, that is,

I D   =   1 2 k p ( W L )   V O V 2 = 1 2 × 1 0 0 × 1 0 × 0. 2 2 = 2 0  μ A

Thus,

r o = 1 0.2 × 2 0 = 0.2 5  M Ω

(f)

I D = 1 2 k p ( W L ) V O V 2 ( 1 + λ V S D )

At V D = 1 V, we have V S D = 1.8 1 = 0.8 V, and I D = 1 2 × 1 0 0 × 1 0 × 0. 2 2 ( 1 + 0.2 × 0.8 ) = 2 3.2  μ A.

At V D = 0 V, we get V S D = 1.8 0 = 1.8 V, and I D = 1 2 × 1 0 0 × 1 0 × 0. 2 2 ( 1 + 0.2 × 1.8 ) = 2 7.2  μ A

Thus, for

V S D = 1.8 0.8 = 1  V ,

the current changes by

I D = 2 7.2 2 3.2 = 4  μ A

indicating that the output resistance r o is

r o = V D I D = 1  V 4  μ A = 0.2 5  M Ω

which is the same value found in (e).


Section 5.3: MOSFET Circuits at DC

D5.7

Alt text

Figure 5.7.1

Alt text

Figure 5.7.2

The NMOS transistor in the circuit in Fig. 5.7.1 has V t n = 0.5 V, k n ' = 4 0 0  μA/V 2, W L = 1 0, and λ = 0.
(a) Design the circuit (i.e., find the required values for R S and R D) to obtain I D = 1 8 0 μA and V D = + 0.5 V. Find the voltage V S that results.
(b) If R S is replaced with a constant-current source I, as shown in Fig. 5.7.2, what must the value of I be to obtain the same operating conditions as in (a)?
(c) What is the largest value to which R D can be increased while the transistor remains in saturation?

Alt text

Figure 5.7.1

(a) Refer to the circuit in Fig 5.7.1. For V D = + 0.5 V, the transistor is operating in saturation since V >  V G. Thus,

I D = 1 2 k n ( W L ) V O V 2

where we have utilized the given information that λ = 0. To obtain I D = 1 8 0  μ A, the required V O V can be found from

1 8 0   =   1 2 × 4 0 0 × 1 0 V O V 2 V O V = 0.3  V

The value of V G S can be found as

V G S = V t n + V O V = 0.5 + 0.3 = 0.8  V

from which V S can be determined as

V S = V G V G S = 0 0.8 = 0.8  V

The required value of R S can now be found from

R S   =   V S     ( V S S ) I D = 0.8     ( 1 ) 1 8 0  μ A = 0.2  V 0.1 8  mA = 1.1 1  k Ω

Finally, the value of R D can be found from

R D   =   V D D     V D I D = 1     0.5 0.1 8  mA = 2.7 8  k Ω

Alt text

Figure 5.7.3

Figure 5.7.3 shows the designed circuit with the component values and the values of current and voltages.
(b) If R S is replaced by a constant-current source I, as shown in Fig. 5.7.2, the value of I must be equal to the desired value of I D, that is, 1 8 0  μ A or 0.1 8  mA.

Alt text

Figure 5.7.2

(c) Refer to Fig. 5.7.1.
As R D is increased, V D decreases as

V D   =   1 I D R D = 1 0.18 R D

Eventually, V D falls below V G by V t n at which point the transistor leaves the saturation region and enters the triode region. This occurs at

V D = V G V t n = 0 0.5 = 0.5  V

The corresponding value of R D can be found from

0.5   =   1 0.1 8 × R D R D = 8.3 3  k Ω

D5.8

Alt text

Figure 5.8.1

The PMOS transistor in the circuit in Fig. 5.8.1 has V t p = 0.5 V, k p ' = 1 0 0  μA/V 2, W L = 2 0, and λ = 0.
(a) Find R S and R D to obtain I D = 0.1 mA and V D = 0 V.
(b) What is the largest R D for which the transistors remains in saturation. At this value of R D, what is the voltage at the drain, V D?

Alt text

Figure 5.8.1

(a) With V D = 0 V, the transistor will be operating in the saturation region since V D = V G. Thus,

I D = 1 2 k p ( W L )   V O V 2

where we have taken into account that λ = 0 as stated. To obtain I D = 0.1  mA = 1 0 0  μ A, the required value of V O V can be found as follows:

1 0 0   =   1 2 × 1 0 0 × 2 0 V O V 2 V O V = 0.3 1 6  V

The value of V S G can now be found as

V S G = V t p + V O V = 0.5 + 0.3 1 6 = 0.8 1 6  V

Thus,

V S = V S G = 0.8 1 6  V

The required value of R S can be determined from

R S   =   V D D  −  V S I D = 1  −  0.8 1 6 0.1 = 1.8 4  k Ω

Finally, the required value of R D can be found from

R D   =   V D  −  ( V S S ) I D = 0  −  ( 1 ) 0.1 = 1 0  k Ω

The designed circuit with component values and current and voltage values is shown in Figure 5.8.2. The reader can check the calculations directly on the circuit diagram.

Alt text

Figure 5.8.2

(b) Refer to Figure 5.8.1. The transistor remains in saturation as long as V D does not increase above V G by more than V t p . Since V G = 0 and V t p = 0.5 V, the maximum allowable value of V D is

V D max = + 0.5  V

To obtain this value of V D, R D must be increased to

R D = V D  max ( 1 ) 0.1  mA = 0.5 + 1 0.1 = 1 5  k Ω

5.9

Alt text

Figure 5.9.1

The NMOS transistor in the circuit in Fig. 5.9.1 has V t = 0.5 V, k n = 1 0 mA/V 2, and λ = 0. Analyze the circuit to determine the currents through all branches and to find the voltages at all nodes.

5.9

Alt text

Figure 5.9.1

The current I through the voltage divider R G 1 R G 2 can be found as

I   =   V D D R G 1 + R G 2 = 5  V 3  M Ω + 2  M Ω = 5  V 5  M Ω = 1  μ A

The voltage V G at the gate can now be found as

V G = I R G 2 = 1  μ A × 2  M Ω = 2  V

The voltage V S is given by

V S   =   V G V G S = V G ( V t + V O V ) = 2 ( 0.5 + V O V )

V S = 1.5 V O V
(1)

But V S can be expressed in terms of I D as

V S = I D R S = I D × 6.5 = 6.5 I D

Thus,

6.5 I D = 1.5 V O V
(2)

We do not know whether the transistor is operating in the saturation region or in the triode region. Therefore, we must make an assumption about the region of operation, complete the analysis, and then use the results obtained to check the validity of our assumption. If our assumption proves valid, our work is done. Otherwise, we must redo the analysis assuming the other mode of operation. Since the i- v relationships that describe the saturation-region operation are simpler than those that apply in the triode region, we normally assume operation in the saturation region, unless of course there is an indication of triode-mode operation.

Assuming that the transistor in the circuit of Figure 5.9.1 is operating in saturation, we can write

I D = 1 2 k n V O V 2 = 1 2 × 1 0 V O V 2
I D = 5 V O V 2
(3)

Substituting for I D from Eq. (3) into Eq. (2) gives

6.5 × 5 V O V 2 = 1.5 V O V

which can be rearranged into the form

3 2.5 V O V 2 + V O V 1.5 = 0

Solving this quadratic equation yields

V O V = 0.2  V  or 0.2 3  V

Obviously, the negative value is physically meaningless and can be discarded. Thus,

V O V = 0.2  V

and

I D = 5 V O V 2 = 5 × 0. 2 2 = 0.2  mA

We are now ready to check the validity of our assumption of saturation mode operation. Referring to the circuit in Figure 5.9.1, we can find the voltage V D as follows:

V D   =   V D D I D R D = 5 0.2 × 1 2.5 = 2.5  V

which is greater than V G ( 2  V ) confirming that the transistor is operating in saturation, as assumed. Figure 5.9.2 shows the circuit together with the values of all node voltages and branch currents. The reader is encouraged to check their results by doing a few calculations directly on the circuit.

Alt text

Figure 5.9.2


5.10

Alt text

Figure 5.10.1

For the circuit in Fig. 5.10.1, the NMOS transistor has V t n = 0.5 V, k n = 1 0 mA/V 2, and λ n = 0, and the PMOS transistor has V t p = 0.5 V, k p = 1 2.5 mA/V 2, and λ p = 0. Observe that Q 1 and its surrounding circuit is the same as the circuit analyzed in Problem 5.9 (Fig. 5.9.1), and you may use the results found in the solution to that problem here. Analyze the circuit to determine the currents in all branches and the voltages at all nodes.

5.10

From Fig. 5.10.1 in the problem statement we observe that transistor Q 1 together with its associated resistors is an identical circuit to that analyzed in the solution to Problem 5.9 (see Fig. 5.9.1). Since the gate terminal of Q 2 draws zero current, transistor Q 2 together with its associated resistances do not change the currents and voltages in Q 1 and its associated resistances. Thus, we need to only concern ourselves with the analysis of the part of the circuit shown in Figure 5.10.2, where V G S is found from

V G 2 = V D 1 = 2.5  V

Alt text

Figure 5.10.2

Since we do not know whether Q 2 is operating in saturation or in the triode region, we shall assume saturation-mode operation and, of course, we will have to check the validity of this assumption. We can now write

I D 2   =   1 2 k p V O V 2 2   =   1 2 × 12.5 V O V 2 2

Thus,

I D 2 = 6.2 5 V O V 2 2 ,  mA
(1)

Another relationship between I D 2 and V O V 2 can be obtained as follows:

V S 2   =   V G 2 + V S G 2 = V G 2 + ( V t p + V O V 2 ) = 2.5 + 0.5 + V O V 2 = 3 + V O V 2

But

I D 2   =   V D D - V S 2 R S 2   =   5 - ( 3 + V O V 2 ) 7.2 I D 2   =   2 - V O V 2 7.2 ,   m A
(2)

Equating I D 2 from Eqs. (1) and (2) results in

6.25 V O V 2 2 = 2 V O V 2 7.2

which can be rearranged into the form

45 V O V 2 2 + V O V 2 2 = 0

This quadratic equation can be solved to obtain

V O V 2 = 0.2  V  or 0.2 2  V

Obviously, the negative solution is physically meaningless, thus

V O V 2 = 0.2  V

and

I D 2 = 6.2 5 × 0. 2 2 = 0.2 5  mA

We are now ready to check the validity of our assumption of saturation-mode operation. We can do this by finding V D 2:

V D 2 = I D 2 R D 2 = 0.2 5 × 8 = 2  V

which is lower than the voltage at the gate ( V G2 = 2.5 V), confirming saturation-mode operation. The voltage V S2 can be found as

V S 2 = V D D I D 2 R S 2 = 5 0.2 5 × 7.2 = + 3.2  V

Alt text

Figure 5.10.3

Finally, Fig. 5.10.3 shows the complete circuit with all currents and voltages. The values associated with Q 1 are those obtained in the solution for Problem 5.9. The reader is urged to make a few quick checks on the results displayed in Fig. 5.10.3.


D5.11

Alt text

Figure 5.11.1

Design the circuit in Fig. 5.11.1 to obtain I = 1  μA, I D = 0.5 mA, V S = 2 V, and V D = 5 V. The NMOS transistor has V t = 0.5 V, k n = 4 mA/V 2, and λ = 0.

5.11

Alt text

Figure 5.11.1

Refer to Fig. 5.11.1. We assume that the transistor is operating in the saturation mode, thus

I D = 1 2 k n V O V 2

where we have taken account of the stated value λ = 0. To obtain I D = 0.5 mA, the required value of V O V can be found from

0.5   =   1 2 × 4 V O V 2 V O V = 0.5  V

Now, since

V D S = V D V S = 5 2 = 3  V

is greater than V O V , the MOSFET is operating in saturation, as assumed. The required value of R S can be determined as follows:

R S = V S I D = 2 0.5 = 4  k Ω

and the required value of R D can be determined as follows:

R D = V D D V D I D = 1 0 5 0.5 = 1 0  k Ω

The voltage at the gate V G is found as

V G = V G S + V S

where

V G S = V t + V O V = 0.5 + 0.5 = 1  V

Thus,

V G = 1 + 2 = 3  V

The resistance R G 1 can be found as follows:

R G 1 = V D D V G I = 1 0 3 1 μ A = 7  M Ω

and, finally, R G 2 can be found as

R G 2 = V G I = 3  V 1 μ A = 3  M Ω

5.12

Alt text

Figure 5.12.1

The transistors in the circuits of Fig. 5.12.1 have V t = 0.5 V, k n = k p = 2 0 mA/V 2, and λ = 0. Also, I = 0.9 mA. For each circuit find v O as a function of v I assuming the transistors are operating in saturation. In each case find the allowable ranges of v O and v I. Assume that the minimum voltage V C S required across each current source is 0.3 V.

5.12

(a)

Alt text

Figure 5.12.1(a)

v O = v I V G S

where

V G S = V t + V O V

and V O V can be found from

I D = I = 1 2 k n V O V 2

Thus,

0.9   =   1 2 × 2 0 V O V 2 V O V = 0.3  V

and

V G S = 0.5 + 0.3 = 0.8  V

Thus,

v O = v I 0.8
(1)

The highest value that v O can have while the transistor remains in saturation is limited by the need to keep v D S at least equal to V O V , thus

v O max = 2.5 V O V = 2.2  V

The lowest value that v O can have is limited by the need to keep the voltage across the current source V C S at least equal to 0.3 V, thus

v O min = 2.5 + 0.3 = 2.2  V

Thus, the allowable range of v O is

2.2  V v O + 2.2  V

and the corresponding allowable range of v I can be found using Eq. (1) as

1.4  V v I + 3  V

(b)

Alt text

Figure 5.12.1(b)

v O = v I + V S G

where

V S G = V t + V O V

and V O V can be found from

I D   =   I = 1 2 k p V O V 2 0.9 = 1 2 × 2 0 V O V 2 V O V = 0.3  V

Thus,

V S G = 0.5 + 0.3 = 0.8  V

and,

v O = v I + 0.8
(2)

The highest value that v O can have is limited by the need to keep the voltage V C S across the current source to at least 0.3 V, thus

v O max = 2.5 0.3 = 2.2  V

The lowest value that v O can have is limited by the need to keep the voltage v S D to a value at least equal to V O V , thus

v O min = 2.5 + 0.3 = 2.2  V

Thus, the allowable range of v O is

2.2  V v O + 2.2  V

The corresponding range of v I can be determined using Eq. (2) as

3  V v I + 1.4  V

(c)

Alt text

Figure 5.12.1(c)

From the results of (a) and (b), we know that

V G S 1 = V S G 2 = 0.8  V

The voltage v O can be found as follows:

v O   =   v I V G S 1 + V G S 2 = v I 0.8 + 0.8

Thus,

v O = v I
(3)

The highest value of v O is determined by the need to keep the voltage V C S across the current source I of Q 2 at least equal to 0.3 V. Thus,

v O max = 2.5 0.3 = + 2.2  V

At this value, the voltage at the source of Q 1 is

v S 1 = 2.2 0.8 = + 1.4  V

which is an allowed value as we determined in (a) above.

The lowest value of v O can be determined by the need to maintain a minimum v S D across Q 2 of value equal to V O V = 0.3 V. This would imply that v O can be as low as 2.5 + 0.3 = 2.2 V. However, v O = 2.2 V would require v S 1 to be v S 1 = 2.2 V S G = 2.2 0.8 = 3 V, which is not within the allowable range for v S 1 [see (a) above]. It follows that the lowest allowable value of v O is determined by the lowest allowable value at the source of Q 1:

v O min   =   v S 1 min + V S G = 2.2 + 0.8 = 1.4  V

Thus, the allowable range of v O is

1.4  V v O + 2.2  V

and using Eq. (3), the allowable range of v I can be found as

1.4  V v I 2.2  V

(d)

Alt text

Figure 5.12.1(d)

Following a procedure identical to that we used for (c) above, we can show that here

v O = v I
(4)

and that the allowable range at the output is

2.2  V v O + 1.4  V

and at the input

2.2  V v I + 1.4  V